Along with the miniaturization, high integration and high structural complexity of semiconductor devices, a failure analysis thereof has become an increasingly difficult task. Generally, in a memory device, bit pass/fail data (Fail Bit) is collected by a semiconductor test device and an FBM (fail bit map) is generated to make an analysis thereof. A logical address of a fail bit collected by the test device is converted into a physical address, FBM image data is generated based on the conversion result, and the generated FBM image data is retained. The FBM image data is displayed at the display request of an analyzer. Also, there is a method that analyzes a plurality of FBMs of test patterns and test conditions in an overlapped manner.